A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having ferroelectric capacitors whose upper electrodes are made of conductive oxide and its manufacture method.
B) Description of the Related Art
Ferroelectric memories have drawn attention as non-volatile memories which retain stored data even if a power is turned off. A ferroelectric memory is made of a combination of a MOS transistor and a ferroelectric capacitor whose dielectric film is made of ferroelectric material. Data are stored in the ferroelectric memory as a direction of spontaneous polarization in a ferroelectric film.
With reference to FIGS. 8A to 8C, description will be made on a ferroelectric capacitor manufacture method disclosed in JP-A-2001-127262.
As shown in FIG. 8A, above the surface of an interlayer insulating film formed on a substrate 100, a ferroelectric capacitor is formed which is constituted of a lower electrode 101, a capacitor ferroelectric film 102 and an upper electrode 103. The lower electrode 101 has a two-layer structure of a Ti film and a Pt film stacked in this order from the bottom. The capacitor ferroelectric film 102 is made of ferroelectric material such as (Pb, Zr)TiO3 (hereinafter denoted as “PZT”) and (Pb, Zr)(Ti, La)O3 (hereinafter denoted as “PLZT”). The upper electrode 103 is made of iridium oxide, and a lower layer region 103A has a higher oxygen concentration than that of an upper layer region 103B.
The upper electrode 103 having the two-layer structure can be formed, for example, by sputtering an Ir metal target by plasma of a mixture gas of oxygen and argon. At a plasma generation DC power of 1 kW, the lower layer region 103A is formed having a relatively high oxygen concentration, and at a raised DC power of 2 kW, the upper layer region 103B is formed having a relatively low oxygen concentration. By lowering the oxygen concentration of the upper layer region 103B, it is possible to suppress abnormal growth of giant crystalline grains.
An interlayer insulating film 105 of silicon oxide is formed on the substrate 1, covering the ferroelectric capacitor.
As shown in FIG. 8B, the interlayer insulating film 105 is dry-etched to form via holes 110 and 111. A portion of the upper electrode 103 is exposed on the bottom of the via hole 110, and a portion of the lower electrode 101 is exposed on the bottom of the other via hole 111. After the via holes 110 and 111 are formed, heat treatment is performed for 60 minutes at 550° C. in an oxygen atmosphere to undo defects generated in the capacitor ferroelectric film 102 during dry etching.
As shown in FIG. 8C, a TiN film 115 is formed covering the inner walls of the via holes 110 and 111 and the surface of the interlayer insulating film 105. The TiN film 115 is patterned to form a local wiring pattern.
It is preferable to clean the surfaces of the upper and lower electrodes 103 and 101 exposed on the bottoms of the via holes 110 and 111 shown in FIG. 8C, in order to obtain good electric contacts at the interface between the upper electrode 103 and TiN film 115 and at the interface between the lower electrode 101 and TiN film 115. For example, this cleaning is performed by exposing the substrate surface to argon plasma.
The present inventor has found that as the substrate surface is cleaned, a contact resistance between the upper electrode 103 and TiN film 115 increases in some cases.